When target is another branch • philosophically, delay slots good? (a) what is the number of delay slots needed to ensure correct operation? This might explain all those Green Line delays In boston • we can reduce the impact of control hazards through: Branch delay slots pipeline . However, to understand why we need to learn fundamental concepts such as instruction pipelining and branch prediction. I was puzzled for while by some unexpected assembly produced by gcc while working on my own implementation of the mips isa, further investigation yielded the following results about the branch delay and the load delay slots, both of them occurred in early mips architectures. Instead of addressing each comment, i’ll just make a post out of it. Branch delay slots were intentionally chosen to be a part of the mips isa design. Programmer should try to insert independent instructions in branch delay slots. Jump targets, branch targets and destinations are resolved in the execute stag...
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